Integrated circuit memory devices are widely used in consumer and a commercial applications. More specifically, conventional read/write memory devices such as dynamic random access memory devices (DRAM) are often used as part of a data processing system that includes a central processing unit (CPU). It may be difficult to operate a conventional DRAM at speeds that are compatible with the overall system speed. In order to allow a DRAM to operate at high speed, "synchronous" DRAMs, also referred to as SDRAMs have been developed. A synchronous DRAM can receive a system clock that is synchronous to the processing speed of the overall system. The internal circuitry of the SDRAM can be operated in such a manner as to accomplish read/write operations in synchronism with the system clock. Thus, for example, in an SDRAM, a row active signal and a read/write command may be input in synchronization with the system clock. SDRAMs are described in U.S. Pat. No. 5,610,874 to Park et al. entitled "Fast Burst-Mode Synchronous Random Access Memory Device", assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference.
It is also known to use a data input/output mask (DQM) signal that is applied from external to the integrated circuit, in order to mask output data from the memory cell array during a read operation and to mask input data to the memory cell array during a write operation. More specifically, if the DQM signal is applied when the output data is generated by an output driver during a read operation, the read DQM latency is equal to 2. Accordingly, the second generated output data from the time the DQM signal is applied, is masked. On the other hand, the write DQM latency is equal to 0 during the write operation, to prevent the enabling of a column select line corresponding to an address to which the DQM signal is applied. Accordingly, the writing of data to the corresponding memory cell is masked.
The DQM signal that is applied from external to the integrated circuit, is often a Transistor Transistor Logic (TTL) signal. In contrast, an SDRAM generally includes complementary metal oxide semiconductor (CMOS) logic levels. The TTL DQM signal is converted to CMOS levels using a DQM input buffer that generally includes a differential amplifier. A DQM input buffer that responds to a DQM signal is described in detail in U.S. Pat. No. 5,631,871 to Park et al. entitled "System for Selecting One of a Plurality of Memory Banks for Use in an Active Cycle and All Other Banks For an Inactive Precharge Cycle", assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference. It will also be understood that DQM input buffers and DQM signals may also be used in other integrated circuit memory devices.
The number of data bits that are simultaneously input to or output from an integrated circuit memory device has generally increased as the integration density of memory devices has increased. Accordingly, as the number of data input/output pins increases, the number of DQM input buffers may also generally increase. Due to the increase in the number of DQM input buffers that are present in integrated circuits, the current consumption of the DQM buffers may also increase. Accordingly, it is desirable to reduce the current consumption in the individual DQM input buffers.
FIG. 1 is a schematic block diagram of a conventional SDRAM including a DQM input buffer controller that can reduce the current consumption of an associated DQM input buffer. More specifically, as shown in FIG. 1, a DQM input buffer 11 is responsive to a DQM signal DQM and generates an output signal PDQM that is applied to the memory cell array 13 of the integrated circuit memory device. When the output signal PDQM is active during a read operation, the output of data from the memory cell array 13 of the SDRAM is masked.
As shown in FIG. 1, a controller 15 produces an enable signal EN that is applied to the DQM input buffer 11 to enable and disable the DQM input buffer 11. The controller 15 includes a NOR gate and generates the enable signal EN in response to a refresh signal RFS and a power-down signal PWD.
When either the refresh signal RFS or the power-down signal PWD is activated to logic "high", the enable signal EN becomes logic "low" and the DQM input buffer 11 is disabled. Accordingly, the output signal PDQM of the DQM input buffer 11 becomes inactive. Conversely, when the refresh signal RFS and the powerdown signal PWD are both inactivated to logic "low", the enable signal EN becomes logic "high" and the DQM input buffer 11 is enabled. Thus, the DQM signal can be input to the DQM input buffer 11. In summary, in a conventional SDRAM, when either the refresh signal RFS or the power-down signal PWD becomes active, the DQM input buffer 11 is disabled, thus reducing the current consumption of the DQM input buffer 11.
However, as described above, the number of DQM input buffers in integrated circuit memory devices has continued to increase. Accordingly, it is desirable to further reduce the current consumption in each DQM input buffer.